Programmable logic devices, such as a complex programmable logic device (CPLD), typically include a number of independent logic blocks interconnected by a global or centralized routing structure. For example, FIG. 1 illustrates a block diagram of a conventional CPLD 10 that includes a routing structure 100 and sixteen logic blocks 102, with each logic block 102 having 16 macrocells (not illustrated) and receiving 36 inputs from routing structure 100. The architecture of the logic block and of the routing structure (or interconnect) are two significant factors that determine the density, performance, and scalability of a CPLD.
Each logic block 102 in conventional CPLD 10 includes a programmable AND array (not illustrated) that a user configures to provide product term outputs of the true and complement form of the logical inputs received from routing structure 100. The product terms may be summed and the resulting sum of product terms registered in the macrocells within each logic block 102. The number of logical inputs that may factor into each product term is referred to as the “input width” for a given logic block and is fixed by the routing structure configuration. With respect to FIG. 1, the input width for logic blocks 102 is thirty-six. Another metric for a logic block is its depth, which is determined by the number of product terms that may be summed and registered within each macrocell. Just like the input width, the depth is fixed according to the configuration of a given macrocell.
Users often require relatively wide input logic blocks providing a high density of macrocells to implement complex functions such as decoders. However, as just described, conventional CPLD logic blocks are implemented with a fixed input width such that users may achieve a higher input width only by cascading product terms through the routing structure. Turning now to FIG. 2a, logic block 102a provide a product term having an input width of 36 logical variables to routing structure 100 to be routed to logic block 102b. At logic block 102b, the cascaded product term may be “ANDed” with 35 additional logical inputs to provide a product term having an input width of 71 logical variables. In turn, the product term outputs from logic block 102b may be cascaded through routing structure 100 and “ANDed” with 35 additional logical inputs in logic block 102c to provide a product term output having an input width of 106 logical variables. Finally, the product term output from logic block 102c may be cascaded through routing structure 100 and “ANDed” with 35 additional logical inputs in logic block 102d to provide a product term output having an input width of 141 logical variables.
In a similar fashion, sum of product term outputs may be cascaded through the routing structure to provide greater logic depth. Turning now to FIG. 2b, logic blocks 102a-d each have a fixed product term depth of 80 product terms. Thus, sums of up to 80 product term outputs from logic block 102a may be routed through routing structure 100 to the macrocells (not illustrated) in logic block 102b. In this fashion, sums of up to 160 product term outputs from logic block 102b may be routed through routing structure 100 to logic block 102c, which in turn may provide sums of up to 240 product term outputs to logic block 102d. Logic block 102d may thus provide sums of up to 320 product term outputs.
Although the width and depth cascading discussed with respect to FIGS. 2a and 2b provides greater flexibility to users, this flexibility is associated with routing structure burdens and routing structure delays. Accordingly, there is a need in the art for logic blocks having enhanced width and depth cascading.